SDRAM refers to synchronous dynamic random access memory, a term that is used to describe dynamic random access memory that has a synchronous interface. Traditionally, dynamic random access memory (DRAM) has an asynchronous interface which means that it responds as quickly as possible to changes in control inputs. SDRAM has a synchronous interface, meaning that it waits for a clock signal before responding to control inputs and is therefore synchronized with the computer's system bus. The clock is used to drive an internal finite state machine that pipelines incoming instructions. This allows the chip to have a more complex pattern of operation than asynchronous DRAM which does not have a synchronized interface. Pipelining means that the chip can accept a new instruction before it has finished processing the previous one. In a pipelined write, the write command can be immediately followed by another instruction without waiting for the data to be written to the memory array. In a pipelined read, the requested data appears after a fixed number of clock pulses after the read instruction, cycles during which additional instructions can be sent. (This delay is called the latency and is an important parameter to consider when purchasing SDRAM for a computer.) SDRAM history Although the concept of synchronous DRAM has been known since at least the 1970s and was used with early Intel processors, it was only in 1993 that SDRAM began its path to universal acceptance in the electronics industry. In 1993, Samsung introduced its KM48SL2000 synchronous DRAM, and by 2000, SDRAM had replaced virtually all other types of DRAM in modern computers, because of its greater speed. SDRAM latency is not inherently lower (faster) than asychronous DRAM. Indeed, early SDRAM was somewhat slower than contemporaneous burst EDO DRAM due to the additional logic. The benefits of SDRAM's internal buffering come from its ability to interleave operations to multiple banks of memory, thereby increasing effective bandwidth. Today, virtually all SDRAM is manufactured in compliance with standards established by JEDEC, an electronics industry association that adopts open standards to facilitate interoperability of electronic components. JEDEC formally adopted its first SDRAM standard in 1993 and subsequently adopted other SDRAM standards, including those for DDR, DDR2 and DDR3 SDRAM. SDRAM is also available in registered varieties, for systems that require greater scalability such as servers and workstations. As of 2007, 168-pin SDRAM DIMMs are not used in new PC systems, and 184-pin DDR memory has been mostly superseded. DDR2 SDRAM is the most common type used with new PCs, and DDR3 motherboards and memory are widely available, but more expensive than still-popular DDR2 products. Today, the world's largest manufacturers of SDRAM include: Samsung Electronics, Micron Technology, Qimonda (formerly Infineon Technologies) and Hynix. [edit] SDRAM timing There are several limits on DRAM speed. Most noted is the read cycle time, the time between successive read operations to an open row. This time decreased from 10 ns for 100 MHz SDRAM to 5 ns for DDR-400, but has remained relatively unchanged through DDR2-800 and DDR3-1600 generations. However, by operating the interface circuitry at increasingly higher multiples of the fundamental read rate, the achievable bandwidth has increased rapidly. Another limit is the CAS latency, the time between supplying a column address and receiving the corresponding data. Again, this has remained relatively constant at 10–15 ns through that last few generations of DDR SDRAM. In operation, CAS latency is a specific number of clock cycles programmed into the SDRAM's mode register and expected by the DRAM controller. Any value may be programmed, but the SDRAM will not operate correctly if it is too low. At higher clock rates, the useful CAS latency in clock cycles naturally increases. 10–15 ns is 2–3 cycles (CL2–3) of the 200 MHz clock of DDR-400 SDRAM, CL4-6 for DDR2-800, and CL8-12 for DDR3-1600. Slower clock cycles will naturally allow lower numbers of CAS latency cycles. SDRAM modules have their own timing specifications, which may be slower than those of the chips on the module. When 100 MHz SDRAM chips first appeared, some manufacturers sold "100 MHz" modules that could not reliably operate at that speed. In response, Intel published the PC100 standard, which outlines requirements and guidelines for producing a memory module that can operate reliably at 100 MHz. This standard was widely influential, and the term "PC100" quickly became a common identifier for 100 MHz SDRAM modules, and modules are now commonly designated with "PC"-prefixed numbers (although the actual meaning of the numbers has changed). SDR SDRAM 64 MB sound memory of Sound Blaster X-Fi Fatal1ty Pro uses two Micron 48LC32M8A2-75 C SDRAM chips working at 133MHz/7.5 ns 8-bit wide 64 MB sound memory of Sound Blaster X-Fi Fatal1ty Pro uses two Micron 48LC32M8A2-75 C SDRAM chips working at 133MHz/7.5 ns 8-bit wide [1] Originally simply known as "SDRAM", Single Data Rate SDRAM can accept one command and transfer one word of data per clock cycle. Typical clock frequencies are 100 and 133 MHz. Chips are made with a variety of data bus sizes (most commonly 4, 8 or 16 bits), but chips are generally assembled into 168-pin DIMMs that read or write 64 (non-ECC) or 72 (ECC) bits at a time. Use of the data bus is intricate and requires a complex DRAM controller. This is because data written to the DRAM must be presented in the same cycle as a write command, but reads produce output 2 or 3 cycles after the read command. The DRAM controller must ensure that the data bus is never required for a read and a write at the same time. Typical SDR SDRAM clock speeds are 66, 100, and 133 MHz (15, 10, and 7.5 ns/cycle). Speeds up to 150 MHz were available for overclockers. SDRAM operation A 512 megabyte (i.e., 512 MiB) SDRAM DIMM might be made of 8 or 9 SDRAM chips, each containing 512 Mbit (512 Mibit) of storage, and each one contributing 8 bits to the DIMM's 64- or 72-bit width. A typical 512 Mbit SDRAM chip internally contains 4 independent 16 Mbyte banks. Each bank is an array of 8192 rows of 16384 bits each. A bank is either idle, active, or changing from one to the other. An active command activates an idle bank. It takes a 2-bit bank address (BA0–BA1) and a 13-bit row address (A0–A12), and reads that row into the bank's array of 16384 sense amplifiers. This is also known as "opening" the row. This operation has the side effect of refreshing that row. Once the row has been activated or "opened", read and write commands are possible. Each command requires a column address, but because each chip works on 8 bits at a time, there are 2048 possible column addresses, needing only 11 address lines (A0–A9,A11). Activation requires a minimum time, called the row-to-column delay, or tRCD. This time, rounded up to the next multiple of the clock period, specifies the minimum number of cycles between an active command, and a read or write command. During these delay cycles, arbitrary commands may be sent to other banks; they are completely independent. When a read command is issued, the SDRAM will produce the corresponding output data on the DQ lines in time for the rising edge of the clock 2 or 3 cycles later (depending on the configured CAS latency). Subsequent words of the burst will be produced in time for subsequent rising clock edges. A write command is accompanied by the data to be written on the DQ lines during the same rising edge. It is the duty of the memory controller to ensure that the SDRAM is not driving read data on the DQ lines at the same time that it needs to drive write data on those lines. This can be done by waiting until a read burst is not in progress, terminating the read burst, or using the DQM control line. When the memory controller wants to access a different row, it must first return that bank's sense amplifiers to an idle state, ready to sense the next row. This is known as a "precharge" operation, or "closing" the row. A precharge may be commanded explicitly, or it may be performed automatically at the conclusion of a read or write operation. Again, there is a minimum time, the row precharge delay, tRP, which must elapse before that bank is fully idle and it may receive another active command. Although refreshing a row is an automatic side effect of activating it, there is a minimum time for this to happen, which requires a minimum row access time tRAS, that must elapse between an active command opening a row, and the corresponding precharge command closing it. This limit is usually dwarfed by desired read and write commands to the row, so its value has little effect on typical performance. DDR SDRAM While the access latency of DRAM is fundamentally limited by the DRAM array, DRAM has very high potential bandwidth because each internal read is actually a row of many thousands of bits. To make more of this bandwidth available to users, a Double Data Rate interface was developed. This uses the same commands, accepted once per cycle, but reads or writes two words of data per clock cycle. Some minor changes to the SDR interface timing were made in hindsight, and the supply voltage was reduced from 3.3 to 2.5 V. DDR SDRAM (sometimes called "DDR1" for greater clarity) doubles the minimum read or write unit; every access refers to at least two consecutive words. Typical DDR SDRAM clock speeds are 133, 166 and 200 MHz (7.5, 6, and 5 ns/cycle), generally described as DDR-266, DDR-333 and DDR-400 (3.75, 3, and 2.5 ns per beat). Corresponding 184-pin DIMMS are known as PC2100, PC2700 and PC3200. Speeds up to DDR-550 (PC4400) are available for a price. DDR2 SDRAM DDR2 SDRAM is very similar to DDR SDRAM, but doubles the minimum read or write unit again, to 4 consecutive words. The bus protocol was also simplified to allow higher speed operation. (In particular, the "burst terminate" command is deleted.) This allows the bus speed of the SDRAM to be doubled without increasing the speed of internal RAM operations; instead, internal operations are performed in units 4 times as wide as SDRAM. Also, an extra bank address pin (BA2) was added to allow 8 banks on large RAM chips. Typical DDR2 SDRAM clock speeds are 200, 266, 333 or 400 MHz (5, 3.75, 3 and 2.5 ns/cycle), generally described as DDR2-400, DDR2-533, DDR2-667 and DDR2-800 (2.5, 1.875, 1.5 and 1.25 ns per beat). Corresponding 240-pin DIMMS are known as PC2-3200 through PC2-6400. Speeds up to DDR2-1250 (PC2-10000) are available for a price. Note that because internal operations are at 1/2 the clock rate, DDR2-400 memory (internal clock speed 100 MHz) has somewhat higher latency than DDR-400 (internal clock speed 200 MHz). DDR3 SDRAM DDR3 continues the trend, doubling the minimum read or write unit to 8 consecutive words. This allows another doubling of bandwidth and external bus speed without having to change the speed of internal operations, just the width. DDR3 memory chips are being made commercially [2], and computer systems are available that use them as of the second half of 2007 [3], with expected significant usage in 2008.[4]. Initial speeds were 400 and 533 MHz, which would be described as DDR3-800 and DDR3-1066, but 667 and 800 MHz (DDR3-1333 and DDR3-1600) are now common[5] and speeds up to DDR3-1800 are available for a premium.[6] DDR4 SDRAM DDR4 SDRAM will be the successor to DDR3 SDRAM. It was revealed at the Intel Developer Forum in San Francisco and is currently in the design state and is expected to be released in 2012.[7] The new chips are expected run at 1.2 volts or less,[8][9] versus the 1.5 volts of DDR3 chips and have in excess of 2000 million data transfers per second.